درخواست مقاله

1. The robust-algorithm approach to fault tolerance on processor arrays: fault models, fault diameter, and basic algorithms
Parhami, B.; Chi-Hsiang Yeh;
Parallel Processing Symposium, 1998. 1998 IPPS/SPDP. Proceedings of the First Merged International...and Symposium on Parallel and Distributed Processing 1998
30 March-3 April 1998 Page(s):742 - 746
Digital Object Identifier 10.1109/IPPS.1998.670010
Summary: With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays have been dealt with separately, in that algorithm developers have assumed the availability of complete fault-free arrays and fault tolerance techniques .....
AbstractPlus | Full Text: PDF(668 KB) IEEE CNF
Rights and Permissions
2. The Role of a Maintenance Processor for a General-Purpose Computer System
Liu, T.S.;
Computers, IEEE Transactions on
Volume C-33, Issue 6, June 1984 Page(s):507 - 517
Digital Object Identifier 10.1109/TC.1984.1676474
Summary: Research and development in fault-tolerant computing has shown that a dedicated processor, called a maintenance processor, can efficiently monitor, control, and maintain the operation of its host computer. This paper presents the general system struc.....
AbstractPlus | Full Text: PDF(3643 KB) IEEE JNL
Rights and Permissions
3. Dynamic fault reconfiguration in a mesh-connected MIMD environment
Uyar, M.U.; Reeves, A.P.;
Computers, IEEE Transactions on
Volume 37, Issue 10, Oct. 1988 Page(s):1191 - 1205
Digital Object Identifier 10.1109/12.5981
Summary: The near-neighbor problem is characterized by many iterations of a parallel matrix operation in which each matrix element is recomputed as a function of itself and its immediately adjacent near neighbors. Several highly parallel computer systems have.....
AbstractPlus | Full Text: PDF(1112 KB) IEEE JNL
Rights and Permissions
4. Evaluating MapReduce for Multi-core and Multiprocessor Systems
Ranger, C.; Raghuraman, R.; Penmetsa, A.; Bradski, G.; Kozyrakis, C.;
High Performance Computer Architecture, 2007. HPCA 2007. IEEE 13th International Symposium on
10-14 Feb. 2007 Page(s):13 - 24
Digital Object Identifier 10.1109/HPCA.2007.346181
Summary: This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers with thousands of servers. It allows programmers to write functional-s.....
AbstractPlus | Full Text: PDF(14156 KB) IEEE CNF
Rights and Permissions
5. Implementing halt on failure processors
Macdonald, R.; Shoja, G.;
Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on
Volume 1, 19-21 May 1993 Page(s):272 - 275 vol.1
Digital Object Identifier 10.1109/PACRIM.1993.407171
Summary: The problem of detecting and masking failed processes in a distributed processing environment is considered. The authors propose a virtual halt on failure processor where replicated processes are used to achieve fault tolerance. Processor failures ar.....
AbstractPlus | Full Text: PDF(324 KB) IEEE CNF
Rights and Permissions
6. Algorithm-based fault tolerance on a hypercube multiprocessor
Banerjee, P.; Rahmeh, J.T.; Stunkel, C.; Nair, V.S.; Roy, K.; Balasubramanian, V.; Abraham, J.A.;
Computers, IEEE Transactions on
Volume 39, Issue 9, Sept. 1990 Page(s):1132 - 1145
Digital Object Identifier 10.1109/12.57055
Summary: The design of fault-tolerant hypercube multiprocessor architecture is discussed. The authors propose the detection and location of faulty processors concurrently with the actual execution of parallel applications on the hypercube using a novel scheme.....
AbstractPlus | Full Text: PDF(1284 KB) IEEE JNL
Rights and Permissions
7. Task allocation and reallocation for fault tolerance in multicomputer systems
Chen, C.-I.H.; Cherkassky, V.;
Aerospace and Electronic Systems, IEEE Transactions on
Volume 30, Issue 4, Oct. 1994 Page(s):1094 - 1104
Digital Object Identifier 10.1109/7.328753
Summary: The goal of task allocation in a set of interconnected processors (computers) is to maximize the efficient use of resources and thus reduce the job turnaround time. Proposed is a simple yet effective method to allocate the tasks in multicomputer syst.....
AbstractPlus | Full Text: PDF(908 KB) IEEE JNL
Rights and Permissions
8. New encoding/decoding methods for designing fault-tolerant matrix operations
Tao, D.L.; Hartmann, C.R.P.; Han, Y.S.;
Parallel and Distributed Systems, IEEE Transactions on
Volume 7, Issue 9, Sept. 1996 Page(s):931 - 938
Digital Object Identifier 10.1109/71.536937
Summary: Algorithm-based fault tolerance (ABFT) can provide a low-cost error protection for array processors and multiprocessor systems. Several ABFT techniques (weighted check-sum) have been proposed to design fault-tolerant matrix operations. In these schem.....
AbstractPlus | References | Full Text: PDF(756 KB) IEEE JNL
Rights and Permissions
9. Efficient techniques for the analysis of algorithm-based fault tolerance (ABFT) schemes
Nair, V.S.S.; Abraham, J.A.; Banerjee, P.;
Computers, IEEE Transactions on
Volume 45, Issue 4, April 1996 Page(s):499 - 503
Digital Object Identifier 10.1109/12.494110
Summary: This paper presents a model which can be used to characterize the diagnosability of Algorithm-Based Fault Tolerant (ABFT) systems. In the model, the relationship between processors computing useful data, the output data, and the check processors is d.....
AbstractPlus | References | Full Text: PDF(544 KB) IEEE JNL
Rights and Permissions
10. Evaluating reliability improvements of fault tolerant array processors using algorithm-based fault tolerance
Tao, D.L.; Kantawala, K.;
Computers, IEEE Transactions on
Volume 46, Issue 6, June 1997 Page(s):725 - 730
Digital Object Identifier 10.1109/12.600889
Summary: Algorithm-based fault tolerance (ABFT) is used to provide low-cost error protection for VLSI processor arrays used in real-time digital signal processing. The main objective of incorporating an ABFT technique in a processor array is to improve its re.....
AbstractPlus | References | Full Text: PDF(264 KB) IEEE JNL
Rights and Permissions
11. Connective fault tolerance in multiple bus systems
Hung-Kuei Ku; Hayes, J.P.;
Parallel and Distributed Systems, IEEE Transactions on
Volume 8, Issue 6, June 1997 Page(s):574 - 586
Digital Object Identifier 10.1109/71.595574
Summary: We present an efficient approach to characterizing the fault tolerance of multiprocessor systems that employ multiple shared buses for interprocessor communication. Of concern is connective fault tolerance, which is defined as the ability to maintain.....
AbstractPlus | References | Full Text: PDF(540 KB) IEEE JNL
Rights and Permissions
12. An algorithm-based error detection scheme for the multigrid method
Mishra, A.; Banerjee, P.;
Computers, IEEE Transactions on
Volume 52, Issue 9, Sept. 2003 Page(s):1089 - 1099
Digital Object Identifier 10.1109/TC.2003.1228507
Summary: Algorithm-based fault tolerance (ABFT) is a technique to provide system level error detection and correction on array processors as well as multiprocessors at a low cost. Since the early 1980s the technique has been extensively applied to several lin.....
AbstractPlus | References | Full Text: PDF(859 KB) IEEE JNL
Rights and Permissions
13. A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches
Fukushi, M.; Horiguchi, S.;
Instrumentation and Measurement, IEEE Transactions on
Volume 53, Issue 2, April 2004 Page(s):357 - 367
Digital Object Identifier 10.1109/TIM.2003.822717
Summary: This paper deals with the issue of reconfiguring mesh-connected processor arrays (mesh arrays) in the presence of faulty processors. For massively parallel systems, it has become necessary to develop built-in self-reconfigurable systems that can auto.....
AbstractPlus | References | Full Text: PDF(424 KB) IEEE JNL
Rights and Permissions
14. Algorithm-based checkpoint-free fault tolerance for parallel matrix computations on volatile resources
Zizhong Chen; Dongarra, J.;
Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
25-29 April 2006 Page(s):10 pp.
Digital Object Identifier 10.1109/IPDPS.2006.1639333
Summary: As the size of today's high performance computers increases from hundreds, to thousands, and even tens of thousands of processors, node failures in these computers are becoming frequent events. Although checkpoint/rollback-recovery is the typical tec.....
AbstractPlus | Full Text: PDF(6048 KB) IEEE CNF
Rights and Permissions
15. The design of DIVINE-a distributed virtual interminable environment
Wong, W.H.-L.; Ng, J.K.-Y.; Chun Hung Li;
Advanced Information Networking and Applications, 2003. AINA 2003. 17th International Conference on
27-29 March 2003 Page(s):126 - 131
Digital Object Identifier 10.1109/AINA.2003.1192854
Summary: This paper describes the issues involved in designing and implementing a large-scale cooperative object database server for collaborative virtual environment. Participants presented in the environment may include humans and computer artifacts. The fo.....
AbstractPlus | Full Text: PDF(322 KB) IEEE CNF
Rights and Permissions
16. Analysis of SEU effects in a pipelined processor
Rebaudengo, M.; Sonza Reorda, M.; Violante, M.;
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
8-10 July 2002 Page(s):112 - 116
Digital Object Identifier 10.1109/OLT.2002.1030193
Summary: Modern processors embed features such as pipelined execution units and cache memories that can hardly be controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are no longer suitable fo.....
AbstractPlus | Full Text: PDF(264 KB) IEEE CNF
Rights and Permissions
17. An agent based dynamic load balancing system
Rajagopalan, A.; Hariri, S.;
Autonomous Decentralized Systems, 2000. Proceedings. 2000 International Workshop on
21-23 Sept. 2000 Page(s):164 - 171
Digital Object Identifier 10.1109/IWADS.2000.880903
Summary: High-end workstations being immensely underutilized and a selected few being overloaded reflects on the poor performance of a cluster. Load balancing, assigning each processor workload proportional to its performance capability, could significantly e.....
AbstractPlus | Full Text: PDF(688 KB) IEEE CNF
Rights and Permissions
18. Parallel computation of configuration space on reconfigurable mesh with faults
Jenq, J.J.-F.; Dajin Wang;
Parallel Processing, 2000. Proceedings. 2000 International Workshops on
21-24 Aug. 2000 Page(s):259 - 266
Digital Object Identifier 10.1109/ICPPW.2000.869111
Summary: A reconfigurable mesh (RMESH) can be used to compute robotic paths in the presence of obstacles, where the robot and obstacle images are represented and processed in mesh processors. For a non-point-like robot, we can compute the so-called “con.....
AbstractPlus | Full Text: PDF(524 KB) IEEE CNF
Rights and Permissions
19. Noise reduction in computer process synchronisation
Saha, G.K.;
Electromagnetic Interference and Compatibility '99. Proceedings of the International Conference on
6-8 Dec. 1999 Page(s):443 - 444
Summary: This article describes how to gain a noise tolerable computer process synchronisation (e.g. a mutual exclusion problem in a real time system). The algorithm ensures the avoidance of busy wait for processes while sharing common resources such as disk .....
AbstractPlus | Full Text: PDF(96 KB) IEEE CNF
Rights and Permissions
20. An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors
Chin-Chien Sha; Leavene, R.W.;
VLSI, 1994. 'Design Automation of High Performance VLSI Systems'. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
4-5 March 1994 Page(s):56 - 61
Digital Object Identifier 10.1109/GLSV.1994.289995
Summary: An algorithm is proposed to maintain fault tolerance for a highly reliable FFT processor, even after the processor has been reconfigured (by detecting a single fault). It proves that the concurrent error detection (CED) scheme using: a redundant stag.....
AbstractPlus | Full Text: PDF(436 KB) IEEE CNF
Rights and Permissions
21. An effective approach for achieving fault tolerance in hypercubes
Al-Tawil, K.M.; Avresky, D.R.;
Fault-Tolerant Parallel and Distributed Systems, 1994., Proceedings of IEEE Workshop on
12-14 June 1994 Page(s):113 - 120
Digital Object Identifier 10.1109/FTPDS.1994.494482
Summary: The hypercube network is an attractive structure for parallel processing because of its regularity. The problem of tolerating faulty processors in hypercubes has been studied by many researchers, either by using spares or by reconfiguration. In this .....
AbstractPlus | Full Text: PDF(356 KB) IEEE CNF